PCM leverages the resistance change that occurs in the material -- an alloy of various elements -- when it changes its phase from crystalline (low resistance) – to amorphous – featuring high resistance – to store data bits. In a PCM cell, where a phase-change material is deposited between a top and a bottom electrode, phase change can controllably be induced by applying voltage or current pulses of different strengths. These heat up the material and when distinct temperature thresholds are reached cause the material to change from crystalline to amorphous or vice versa.
In addition, depending on the voltage, more or less material between the electrodes will undergo a phase change, which directly affects the cell's resistance. Scientists exploit that aspect use four distinct resistance levels to store the bit combinations "00", "01" 10" and "11".
The scientists implemented an iterative "write" process to overcome deviations in the resistance due to inherent variability in the memory cells and the phase-change materials:
We apply a voltage pulse based on the deviation from the desired level , measure the resistance. If achieved, we apply another voltage pulse and measure again – until we achieve the exact level.
Worst case Performance:10us 100 times slower than flash memory to get the desired resistance.
For demonstrating reliable read-out of data bits, tackling the problem of resistance drift. Because ofstructural relaxation of the atoms in the amorphous state, the resistance increases over time after the phase change, eventually causing errors in the read-out.
To overcome that issue, the IBM scientists applied an advanced modulation coding technique that is inherently drift-tolerant.
The modulation coding technique is based on the fact that, on average, the relative order of programmed cells with different resistance levels does not change due to drift.
About the Drift Tolerant cells:
The following advantages of substrate bias in n-channel MOS technology.
Advantages include:
Elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger differential data signal on the bit sense lines.
The generator circuit avoids several pit-falls on on-chip V/SUB BB/ generation. Circuit pumps to a known regulated voltage avoiding substrate drift with changes in substrate current resulting from changes in cycle time.
Drift will change device characteristics and degrade storage levels. A unique two-level reference scheme avoids changes in substrate bias voltage that otherwise result from the shift or back bias
In addition, depending on the voltage, more or less material between the electrodes will undergo a phase change, which directly affects the cell's resistance. Scientists exploit that aspect use four distinct resistance levels to store the bit combinations "00", "01" 10" and "11".
The scientists implemented an iterative "write" process to overcome deviations in the resistance due to inherent variability in the memory cells and the phase-change materials:
We apply a voltage pulse based on the deviation from the desired level , measure the resistance. If achieved, we apply another voltage pulse and measure again – until we achieve the exact level.
Worst case Performance:10us 100 times slower than flash memory to get the desired resistance.
For demonstrating reliable read-out of data bits, tackling the problem of resistance drift. Because of
To overcome that issue, the IBM scientists applied an advanced modulation coding technique that is inherently drift-tolerant.
The modulation coding technique is based on the fact that, on average, the relative order of programmed cells with different resistance levels does not change due to drift.
About the Drift Tolerant cells:
The following advantages of substrate bias in n-channel MOS technology.
Advantages include:
Elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger differential data signal on the bit sense lines.
The generator circuit avoids several pit-falls on on-chip V/SUB BB/ generation. Circuit pumps to a known regulated voltage avoiding substrate drift with changes in substrate current resulting from changes in cycle time.
Drift will change device characteristics and degrade storage levels. A unique two-level reference scheme avoids changes in substrate bias voltage that otherwise result from the shift or back bias
